Python unicorn.UC_MODE_ARM Examples
The following are 7
code examples of unicorn.UC_MODE_ARM().
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Example #1
Source File: arm.py From rainbow with GNU Lesser General Public License v3.0 | 6 votes |
def __init__(self, trace=True, sca_mode=False, local_vars={}): super().__init__(trace, sca_mode) self.emu = uc.Uc(uc.UC_ARCH_ARM, uc.UC_MODE_ARM) self.disasm = cs.Cs(cs.CS_ARCH_ARM, cs.CS_MODE_ARM | cs.CS_MODE_THUMB) self.disasm.detail = True self.word_size = 4 self.endianness = "little" self.page_size = self.emu.query(uc.UC_QUERY_PAGE_SIZE) self.page_shift = self.page_size.bit_length() - 1 self.pc = uc.arm_const.UC_ARM_REG_PC known_regs = [i[len('UC_ARM_REG_'):] for i in dir(uc.arm_const) if '_REG' in i] self.reg_map = {r.lower(): getattr(uc.arm_const, 'UC_ARM_REG_'+r) for r in known_regs} self.stubbed_functions = local_vars self.setup(sca_mode) self.reset_stack()
Example #2
Source File: aarch64.py From rainbow with GNU Lesser General Public License v3.0 | 6 votes |
def __init__(self, trace=True, sca_mode=False, local_vars=[]): super().__init__(trace, sca_mode) self.emu = uc.Uc(uc.UC_ARCH_ARM64, uc.UC_MODE_ARM) self.disasm = cs.Cs(cs.CS_ARCH_ARM64, cs.CS_MODE_ARM) self.disasm.detail = True self.word_size = 8 self.endianness = "little" self.page_size = self.emu.query(uc.UC_QUERY_PAGE_SIZE) self.page_shift = self.page_size.bit_length() - 1 self.pc = uc.arm64_const.UC_ARM64_REG_PC known_regs = [i[len('UC_ARM64_REG_'):] for i in dir(uc.arm64_const) if '_REG' in i] self.reg_map = {r.lower(): getattr(uc.arm64_const, 'UC_ARM64_REG_'+r) for r in known_regs} self.stubbed_functions = local_vars self.setup(sca_mode) self.reset_stack()
Example #3
Source File: unicorn_trace.py From bootloader_instrumentation_suite with MIT License | 5 votes |
def __init__(self): Emulator.__init__(self, "ARM64", unicorn.UC_ARCH_ARM64, unicorn.UC_MODE_ARM, "pc", 64, ["sp", "cpsr"]) self.syscall_regnames = map(lambda x: "x%d" % x, range(0, 8)) + ["x8", "pc"] self.stackbot = "fp" self.stacktop = "sp" self.syscall_reg = "x8"
Example #4
Source File: unicorn_trace.py From bootloader_instrumentation_suite with MIT License | 5 votes |
def __init__(self): Emulator.__init__(self, "ARM", unicorn.UC_ARCH_ARM, unicorn.UC_MODE_ARM, "pc", 32, ["sp", "cpsr"]) self.syscall_regnames = map(lambda x: "x%d" % x, range(0, 8)) + ["x7", "pc"] self.stackbot = "fp" self.stacktop = "sp" self.syscall_reg = "x7"
Example #5
Source File: main.py From frick with MIT License | 5 votes |
def __init__(self): super(Arm, self).__init__() self.unicorn_arch = unicorn.UC_ARCH_ARM self.unicorn_mode = unicorn.UC_MODE_ARM self.capstone_arch = capstone.CS_ARCH_ARM self.capstone_mode = capstone.CS_MODE_ARM
Example #6
Source File: main.py From frick with MIT License | 5 votes |
def __init__(self): super(Arm64, self).__init__() self.unicorn_arch = unicorn.UC_ARCH_ARM64 self.unicorn_mode = unicorn.UC_MODE_ARM self.capstone_arch = capstone.CS_ARCH_ARM64 self.capstone_mode = capstone.CS_MODE_ARM
Example #7
Source File: gdb_tools.py From bootloader_instrumentation_suite with MIT License | 4 votes |
def __init__(self, controller, r, stage): # controller.gdb_print("creating longwrite break\n") self.emptywrite = {'start': None, 'end': None, 'pc': None} self.writeinfo = self.emptywrite self.breakaddr = r['breakaddr'] self.contaddr = r['contaddr'] self.writeaddr = r['writeaddr'] self.thumb = r['thumb'] r2.gets(stage.elf, "s 0x%x" % self.writeaddr) if self.thumb: self.emu = unicorn.Uc(unicorn.UC_ARCH_ARM, unicorn.UC_MODE_THUMB) r2.gets(stage.elf, "ahb 16") r2.gets(stage.elf, "e asm.bits=16") self.cs = capstone.Cs(capstone.CS_ARCH_ARM, capstone.CS_MODE_THUMB) else: self.emu = unicorn.Uc(unicorn.UC_ARCH_ARM, unicorn.UC_MODE_ARM) r2.gets(stage.elf, "ahb 32") r2.gets(stage.elf, "e asm.bits=32") self.cs = capstone.Cs(capstone.CS_ARCH_ARM, capstone.CS_MODE_ARM) r2.get(stage.elf, "pdj 1") self.cs.detail = True self.info = staticanalysis.LongWriteInfo(stage.elf, r['start'], r['end'], self.thumb) self.inss = [] self.regs = set() self.bytes = b"" self.dst_addrs = [] self.write_size = r['writesize'] for i in self.info.bbs: self.inss.append(i) bs = i["bytes"].decode("hex") self.bytes += b"%s" % bs ci = next(self.cs.disasm(bs, i["offset"], 1)) if i["offset"] == self.writeaddr: self.write_ins = ci (read, write) = ci.regs_access() for rs in (read, write): self.regs.update([ci.reg_name(rn).encode('ascii') for rn in rs]) self.emu.mem_map(0, 0xFFFFFFFF + 1, unicorn.UC_PROT_ALL) self.emu.mem_write(self.inss[0]["offset"], self.bytes) self.emu.hook_add(unicorn.UC_HOOK_MEM_WRITE, self.write_hook) self.spec = "*(0x%x)" % r['breakaddr'] TargetBreak.__init__(self, self.spec, controller, True, stage, r=r)